Apparatus and method for thermal management in a multi-chip package

ABSTRACT

In an embodiment, a processor includes a first chip of a multi-chip package (MCP). The first chip includes at least one core and first chip temperature control (TC) logic to assert a first power adjustment signal at a second chip of the MCP responsive to an indication that a first chip temperature of the first chip exceeds a first threshold. The processor also includes a conduit that includes a bi-directional pin to couple the first chip to the second chip within the MCP. The conduit is to transport the first power adjustment signal from the first chip to the second chip and the first power adjustment signal is to cause an adjustment of a second chip power consumption of the second chip. Other embodiments are described and claimed.

CLAIM OF PRIORITY

This application is a continuation of U.S. patent application Ser. No.14/554,384, filed Nov. 26, 2014. The content of the above application ishereby incorporated by reference.

TECHNICAL FIELD

Embodiments relate to power management of a system.

BACKGROUND

Advances in semiconductor processing and logic design have permitted anincrease in the amount of logic that may be present on integratedcircuit devices. As a result, computer system configurations haveevolved from a single or multiple integrated circuits in a system tomultiple hardware threads, multiple cores, multiple devices, and/orcomplete systems on individual integrated circuits. Additionally, as thedensity of integrated circuits has grown, the power requirements forcomputing systems (from embedded systems to servers) have alsoescalated. Furthermore, software inefficiencies, and its requirements ofhardware, have also caused an increase in computing device energyconsumption. In fact, some studies indicate that computing devicesconsume a sizeable percentage of the entire electricity supply for acountry, such as the United States of America. As a result, there is avital need for energy efficiency and conservation associated withintegrated circuits. These needs will increase as servers, desktopcomputers, notebooks, Ultrabooks™, tablets, mobile phones, processors,embedded systems, etc. become even more prevalent (from inclusion in thetypical computer, automobiles, and televisions to biotechnology).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a portion of a system in accordance with anembodiment of the present invention.

FIG. 2 is a block diagram of a processor in accordance with anembodiment of the present invention.

FIG. 3 is a block diagram of a multi-domain processor in accordance withanother embodiment of the present invention.

FIG. 4 is an embodiment of a processor including multiple cores.

FIG. 5 is a block diagram of a micro-architecture of a processor core inaccordance with one embodiment of the present invention.

FIG. 6 is a block diagram of a micro-architecture of a processor core inaccordance with another embodiment.

FIG. 7 is a block diagram of a micro-architecture of a processor core inaccordance with yet another embodiment.

FIG. 8 is a block diagram of a micro-architecture of a processor core inaccordance with a still further embodiment.

FIG. 9 is a block diagram of a processor in accordance with anotherembodiment of the present invention.

FIG. 10 is a block diagram of a representative SoC in accordance with anembodiment of the present invention.

FIG. 11 is a block diagram of another example SoC in accordance with anembodiment of the present invention.

FIG. 12 is a block diagram of an example system with which embodimentscan be used.

FIG. 13 is a block diagram of another example system with whichembodiments may be used.

FIG. 14 is a block diagram of a representative computer system.

FIG. 15 is a block diagram of a system in accordance with an embodimentof the present invention.

FIG. 16 is a block diagram of an apparatus, according to embodiments ofthe present invention.

FIG. 17 is a flow diagram of a method, according to embodiments of thepresent invention.

FIG. 18 is a flow diagram of another method, according to embodiments ofthe present invention.

FIG. 19 is a flow diagram of another method, according to embodiments ofthe present invention.

DETAILED DESCRIPTION

Although the following embodiments are described with reference toenergy conservation and energy efficiency in specific integratedcircuits, such as in computing platforms or processors, otherembodiments are applicable to other types of integrated circuits andlogic devices. Similar techniques and teachings of embodiments describedherein may be applied to other types of circuits or semiconductordevices that may also benefit from better energy efficiency and energyconservation. For example, the disclosed embodiments are not limited toany particular type of computer systems. That is, disclosed embodimentscan be used in many different system types, ranging from servercomputers (e.g., tower, rack, blade, micro-server and so forth),communications systems, storage systems, desktop computers of anyconfiguration, laptop, notebook, and tablet computers (including 2:1tablets, phablets and so forth), and may be also used in other devices,such as handheld devices, systems on chip (SoCs), and embeddedapplications. Some examples of handheld devices include cellular phonessuch as smartphones, Internet protocol devices, digital cameras,personal digital assistants (PDAs), and handheld PCs. Embeddedapplications may typically include a microcontroller, a digital signalprocessor (DSP), network computers (NetPC), set-top boxes, network hubs,wide area network (WAN) switches, wearable devices, or any other systemthat can perform the functions and operations taught below. More so,embodiments may be implemented in mobile terminals having standard voicefunctionality such as mobile phones, smartphones and phablets, and/or innon-mobile terminals without a standard wireless voice functioncommunication capability, such as many wearables, tablets, notebooks,desktops, micro-servers, servers and so forth. Moreover, theapparatuses, methods, and systems described herein are not limited tophysical computing devices, but may also relate to softwareoptimizations for energy conservation and efficiency. As will becomereadily apparent in the description below, the embodiments of methods,apparatuses, and systems described herein (whether in reference tohardware, firmware, software, or a combination thereof) are vital to a‘green technology’ future, such as for power conservation and energyefficiency in products that encompass a large portion of the US economy.

Referring now to FIG. 1, shown is a block diagram of a portion of asystem in accordance with an embodiment of the present invention. Asshown in FIG. 1, system 100 may include various components, including aprocessor 110 which as shown is a multicore processor. Processor 110 maybe coupled to a power supply 150 via an external voltage regulator 160,which may perform a first voltage conversion to provide a primaryregulated voltage to processor 110.

As seen, processor 110 may be a single die processor including multiplecores 120 _(a)-120 _(n). In addition, each core may be associated withan integrated voltage regulator (IVR) 125 _(a)-125 _(n) which receivesthe primary regulated voltage and generates an operating voltage to beprovided to one or more agents of the processor associated with the IVR.Accordingly, an IVR implementation may be provided to allow forfine-grained control of voltage and thus power and performance of eachindividual core. As such, each core can operate at an independentvoltage and frequency, enabling great flexibility and affording wideopportunities for balancing power consumption with performance. In someembodiments, the use of multiple IVRs enables the grouping of componentsinto separate power planes, such that power is regulated and supplied bythe IVR to only those components in the group. During power management,a given power plane of one IVR may be powered down or off when theprocessor is placed into a certain low power state, while another powerplane of another IVR remains active, or fully powered.

Still referring to FIG. 1, additional components may be present withinthe processor including an input/output interface 132, another interface134, and an integrated memory controller 136. As seen, each of thesecomponents may be powered by another integrated voltage regulator 125_(x). In one embodiment, interface 132 may be enable operation for anIntel® Quick Path Interconnect (QPI) interconnect, which provides forpoint-to-point (PtP) links in a cache coherent protocol that includesmultiple layers including a physical layer, a link layer and a protocollayer. In turn, interface 134 may communicate via a Peripheral ComponentInterconnect Express (PCIe™) protocol.

Also shown is a power control unit (PCU) 138, which may includehardware, software and/or firmware to perform power managementoperations with regard to processor 110. As seen, PCU 138 providescontrol information to external voltage regulator 160 via a digitalinterface to cause the voltage regulator to generate the appropriateregulated voltage. PCU 138 also provides control information to IVRs 125via another digital interface to control the operating voltage generated(or to cause a corresponding IVR to be disabled in a low power mode). Invarious embodiments, PCU 138 may include a variety of power managementlogic units to perform hardware-based power management. Such powermanagement may be wholly processor controlled (e.g., by variousprocessor hardware, and which may be triggered by workload and/or power,thermal or other processor constraints) and/or the power management maybe performed responsive to external sources (such as a platform ormanagement power management source or system software).

While not shown for ease of illustration, understand that additionalcomponents may be present within processor 110 such as uncore logic, andother components such as internal memories, e.g., one or more levels ofa cache memory hierarchy and so forth. Furthermore, while shown in theimplementation of FIG. 1 with an integrated voltage regulator,embodiments are not so limited.

Note that the power management techniques described herein may beindependent of and complementary to an operating system (OS)-based powermanagement (OSPM) mechanism. According to one example OSPM technique, aprocessor can operate at various performance states or levels, so-calledP-states, namely from P0 to PN. In general, the P1 performance state maycorrespond to the highest guaranteed performance state that can berequested by an OS. In addition to this P1 state, the OS can furtherrequest a higher performance state, namely a P0 state. This P0 state maythus be an opportunistic or turbo mode state in which, when power and/orthermal budget is available, processor hardware can configure theprocessor or at least portions thereof to operate at a higher thanguaranteed frequency. In many implementations a processor can includemultiple so-called bin frequencies above the P1 guaranteed maximumfrequency, exceeding to a maximum peak frequency of the particularprocessor, as fused or otherwise written into the processor duringmanufacture. In addition, according to one OSPM mechanism, a processorcan operate at various power states or levels. With regard to powerstates, an OSPM mechanism may specify different power consumptionstates, generally referred to as C-states, C0, C1 to Cn states. When acore is active, it runs at a C0 state, and when the core is idle it maybe placed in a core low power state, also called a core non-zero C-state(e.g., C1-C6 states), with each C-state being at a lower powerconsumption level (such that C6 is a deeper low power state than C1, andso forth).

Understand that many different types of power management techniques maybe used individually or in combination in different embodiments. Asrepresentative examples, a power controller may control the processor tobe power managed by some form of dynamic voltage frequency scaling(DVFS) in which an operating voltage and/or operating frequency of oneor more cores or other processor logic may be dynamically controlled toreduce power consumption in certain situations. In an example, DVFS maybe performed using Enhanced Intel SpeedStep™ technology available fromIntel Corporation, Santa Clara, Calif., to provide optimal performanceat a lowest power consumption level. In another example, DVFS may beperformed using Intel TurboBoost™ technology to enable one or more coresor other compute engines to operate at a higher than guaranteedoperating frequency based on conditions (e.g., workload andavailability).

Another power management technique that may be used in certain examplesis dynamic swapping of workloads between different compute engines. Forexample, the processor may include asymmetric cores or other processingengines that operate at different power consumption levels, such that ina power constrained situation, one or more workloads can be dynamicallyswitched to execute on a lower power core or other compute engine.Another exemplary power management technique is hardware duty cycling(HDC), which may cause cores and/or other compute engines to beperiodically enabled and disabled according to a duty cycle, such thatone or more cores may be made inactive during an inactive period of theduty cycle and made active during an active period of the duty cycle.Although described with these particular examples, understand that manyother power management techniques may be used in particular embodiments.

Embodiments can be implemented in processors for various marketsincluding server processors, desktop processors, mobile processors andso forth. Referring now to FIG. 2, shown is a block diagram of aprocessor in accordance with an embodiment of the present invention. Asshown in FIG. 2, processor 200 may be a multicore processor including aplurality of cores 210 _(a)-210 _(n). In one embodiment, each such coremay be of an independent power domain and can be configured to enter andexit active states and/or maximum performance states based on workload.The various cores may be coupled via an interconnect 215 to a systemagent or uncore 220 that includes various components. As seen, theuncore 220 may include a shared cache 230 which may be a last levelcache. In addition, the uncore may include an integrated memorycontroller 240 to communicate with a system memory (not shown in FIG.2), e.g., via a memory bus. Uncore 220 also includes various interfaces250 and a power control unit 255, which may include logic to perform thepower management techniques described herein.

In addition, by interfaces 250 a-250 n, connection can be made tovarious off-chip components such as peripheral devices, mass storage andso forth. While shown with this particular implementation in theembodiment of FIG. 2, the scope of the present invention is not limitedin this regard.

Referring now to FIG. 3, shown is a block diagram of a multi-domainprocessor in accordance with another embodiment of the presentinvention. As shown in the embodiment of FIG. 3, processor 300 includesmultiple domains. Specifically, a core domain 310 can include aplurality of cores 310 ₀-310 _(n), a graphics domain 320 can include oneor more graphics engines, and a system agent domain 350 may further bepresent. In some embodiments, system agent domain 350 may execute at anindependent frequency than the core domain and may remain powered on atall times to handle power control events and power management such thatdomains 310 and 320 can be controlled to dynamically enter into and exithigh power and low power states. Each of domains 310 and 320 may operateat different voltage and/or power. Note that while only shown with threedomains, understand the scope of the present invention is not limited inthis regard and additional domains can be present in other embodiments.For example, multiple core domains may be present each including atleast one core.

In general, each core 310 may further include low level caches inaddition to various execution units and additional processing elements.In turn, the various cores may be coupled to each other and to a sharedcache memory formed of a plurality of units of a last level cache (LLC)340 ₀-340 _(n). In various embodiments, LLC 340 may be shared amongstthe cores and the graphics engine, as well as various media processingcircuitry. As seen, a ring interconnect 330 thus couples the corestogether, and provides interconnection between the cores, graphicsdomain 320 and system agent circuitry 350. In one embodiment,interconnect 330 can be part of the core domain. However in otherembodiments the ring interconnect can be of its own domain.

As further seen, system agent domain 350 may include display controller352 which may provide control of and an interface to an associateddisplay. As further seen, system agent domain 350 may include a powercontrol unit 355 which can include logic to perform the power managementtechniques described herein.

As further seen in FIG. 3, processor 300 can further include anintegrated memory controller (IMC) 370 that can provide for an interfaceto a system memory, such as a dynamic random access memory (DRAM).Multiple interfaces 380 ₀-380 _(n) may be present to enableinterconnection between the processor and other circuitry. For example,in one embodiment at least one direct media interface (DMI) interfacemay be provided as well as one or more PCIe™ interfaces. Still further,to provide for communications between other agents such as additionalprocessors or other circuitry, one or more QPI interfaces may also beprovided. Although shown at this high level in the embodiment of FIG. 3,understand the scope of the present invention is not limited in thisregard.

Referring to FIG. 4, an embodiment of a processor including multiplecores is illustrated. Processor 400 includes any processor or processingdevice, such as a microprocessor, an embedded processor, a digitalsignal processor (DSP), a network processor, a handheld processor, anapplication processor, a co-processor, a system on a chip (SoC), orother device to execute code. Processor 400, in one embodiment, includesat least two cores—cores 401 and 402, which may include asymmetric coresor symmetric cores (the illustrated embodiment). However, processor 400may include any number of processing elements that may be symmetric orasymmetric.

In one embodiment, a processing element refers to hardware or logic tosupport a software thread. Examples of hardware processing elementsinclude: a thread unit, a thread slot, a thread, a process unit, acontext, a context unit, a logical processor, a hardware thread, a core,and/or any other element, which is capable of holding a state for aprocessor, such as an execution state or architectural state. In otherwords, a processing element, in one embodiment, refers to any hardwarecapable of being independently associated with code, such as a softwarethread, operating system, application, or other code. A physicalprocessor typically refers to an integrated circuit, which potentiallyincludes any number of other processing elements, such as cores orhardware threads.

A core often refers to logic located on an integrated circuit capable ofmaintaining an independent architectural state, wherein eachindependently maintained architectural state is associated with at leastsome dedicated execution resources. In contrast to cores, a hardwarethread typically refers to any logic located on an integrated circuitcapable of maintaining an independent architectural state, wherein theindependently maintained architectural states share access to executionresources. As can be seen, when certain resources are shared and othersare dedicated to an architectural state, the line between thenomenclature of a hardware thread and core overlaps. Yet often, a coreand a hardware thread are viewed by an operating system as individuallogical processors, where the operating system is able to individuallyschedule operations on each logical processor.

Physical processor 400, as illustrated in FIG. 4, includes two cores,cores 401 and 402. Here, cores 401 and 402 are considered symmetriccores, i.e., cores with the same configurations, functional units,and/or logic. In another embodiment, core 401 includes an out-of-orderprocessor core, while core 402 includes an in-order processor core.However, cores 401 and 402 may be individually selected from any type ofcore, such as a native core, a software managed core, a core adapted toexecute a native instruction set architecture (ISA), a core adapted toexecute a translated ISA, a co-designed core, or other known core. Yetto further the discussion, the functional units illustrated in core 401are described in further detail below, as the units in core 402 operatein a similar manner.

As depicted, core 401 includes two hardware threads 401 a and 401 b,which may also be referred to as hardware thread slots 401 a and 401 b.Therefore, software entities, such as an operating system, in oneembodiment potentially view processor 400 as four separate processors,i.e., four logical processors or processing elements capable ofexecuting four software threads concurrently. As alluded to above, afirst thread is associated with architecture state registers 401 a, asecond thread is associated with architecture state registers 401 b, athird thread may be associated with architecture state registers 402 a,and a fourth thread may be associated with architecture state registers402 b. Here, each of the architecture state registers (401 a, 401 b, 402a, and 402 b) may be referred to as processing elements, thread slots,or thread units, as described above. As illustrated, architecture stateregisters 401 a are replicated in architecture state registers 401 b, soindividual architecture states/contexts are capable of being stored forlogical processor 401 a and logical processor 401 b. In core 401, othersmaller resources, such as instruction pointers and renaming logic inallocator and renamer block 430 may also be replicated for threads 401 aand 401 b. Some resources, such as re-order buffers inreorder/retirement unit 435, ILTB 420, load/store buffers, and queuesmay be shared through partitioning. Other resources, such as generalpurpose internal registers, page-table base register(s), low-leveldata-cache and data-TLB 415, execution unit(s) 440, and portions ofout-of-order unit 435 are potentially fully shared.

Processor 400 often includes other resources, which may be fully shared,shared through partitioning, or dedicated by/to processing elements. InFIG. 4, an embodiment of a purely exemplary processor with illustrativelogical units/resources of a processor is illustrated. Note that aprocessor may include, or omit, any of these functional units, as wellas include any other known functional units, logic, or firmware notdepicted. As illustrated, core 401 includes a simplified, representativeout-of-order (OOO) processor core. But an in-order processor may beutilized in different embodiments. The OOO core includes a branch targetbuffer 420 to predict branches to be executed/taken and aninstruction-translation buffer (I-TLB) 420 to store address translationentries for instructions.

Core 401 further includes decode module 425 coupled to fetch unit 420 todecode fetched elements. Fetch logic, in one embodiment, includesindividual sequencers associated with thread slots 401 a, 401 b,respectively. Usually core 401 is associated with a first ISA, whichdefines/specifies instructions executable on processor 400. Oftenmachine code instructions that are part of the first ISA include aportion of the instruction (referred to as an opcode), whichreferences/specifies an instruction or operation to be performed. Decodelogic 425 includes circuitry that recognizes these instructions fromtheir opcodes and passes the decoded instructions on in the pipeline forprocessing as defined by the first ISA. For example, decoders 425, inone embodiment, include logic designed or adapted to recognize specificinstructions, such as transactional instruction. As a result of therecognition by decoders 425, the architecture or core 401 takesspecific, predefined actions to perform tasks associated with theappropriate instruction. It is important to note that any of the tasks,blocks, operations, and methods described herein may be performed inresponse to a single or multiple instructions; some of which may be newor old instructions.

In one example, allocator and renamer block 430 includes an allocator toreserve resources, such as register files to store instructionprocessing results. However, threads 401 a and 401 b are potentiallycapable of out-of-order execution, where allocator and renamer block 430also reserves other resources, such as reorder buffers to trackinstruction results. Unit 430 may also include a register renamer torename program/instruction reference registers to other registersinternal to processor 400. Reorder/retirement unit 435 includescomponents, such as the reorder buffers mentioned above, load buffers,and store buffers, to support out-of-order execution and later in-orderretirement of instructions executed out-of-order.

Scheduler and execution unit(s) block 440, in one embodiment, includes ascheduler unit to schedule instructions/operation on execution units.For example, a floating point instruction is scheduled on a port of anexecution unit that has an available floating point execution unit.Register files associated with the execution units are also included tostore information instruction processing results. Exemplary executionunits include a floating point execution unit, an integer executionunit, a jump execution unit, a load execution unit, a store executionunit, and other known execution units.

Lower level data cache and data translation buffer (D-TLB) 450 arecoupled to execution unit(s) 440. The data cache is to store recentlyused/operated on elements, such as data operands, which are potentiallyheld in memory coherency states. The D-TLB is to store recentvirtual/linear to physical address translations. As a specific example,a processor may include a page table structure to break physical memoryinto a plurality of virtual pages.

Here, cores 401 and 402 share access to higher-level or further-outcache 410, which is to cache recently fetched elements. Note thathigher-level or further-out refers to cache levels increasing or gettingfurther away from the execution unit(s). In one embodiment, higher-levelcache 410 is a last-level data cache—last cache in the memory hierarchyon processor 400—such as a second or third level data cache. However,higher level cache 410 is not so limited, as it may be associated withor includes an instruction cache. A trace cache—a type of instructioncache—instead may be coupled after decoder 425 to store recently decodedtraces.

In the depicted configuration, processor 400 also includes bus interfacemodule 405 and a power controller 460, which may perform powermanagement in accordance with an embodiment of the present invention. Inthis scenario, bus interface 405 is to communicate with devices externalto processor 400, such as system memory and other components.

A memory controller 470 may interface with other devices such as one ormany memories. In an example, bus interface 405 includes a ringinterconnect with a memory controller for interfacing with a memory anda graphics controller for interfacing with a graphics processor. In anSoC environment, even more devices, such as a network interface,coprocessors, memory, graphics processor, and any other known computerdevices/interface may be integrated on a single die or integratedcircuit to provide small form factor with high functionality and lowpower consumption.

Referring now to FIG. 5, shown is a block diagram of amicro-architecture of a processor core in accordance with one embodimentof the present invention. As shown in FIG. 5, processor core 500 may bea multi-stage pipelined out-of-order processor. Core 500 may operate atvarious voltages based on a received operating voltage, which may bereceived from an integrated voltage regulator or external voltageregulator.

As seen in FIG. 5, core 500 includes front end units 510, which may beused to fetch instructions to be executed and prepare them for use laterin the processor pipeline. For example, front end units 510 may includea fetch unit 501, an instruction cache 503, and an instruction decoder505. In some implementations, front end units 510 may further include atrace cache, along with microcode storage as well as a micro-operationstorage. Fetch unit 501 may fetch macro-instructions, e.g., from memoryor instruction cache 503, and feed them to instruction decoder 505 todecode them into primitives, i.e., micro-operations for execution by theprocessor.

Coupled between front end units 510 and execution units 520 is anout-of-order (OOO) engine 515 that may be used to receive themicro-instructions and prepare them for execution. More specifically OOOengine 515 may include various buffers to re-order micro-instructionflow and allocate various resources needed for execution, as well as toprovide renaming of logical registers onto storage locations withinvarious register files such as register file 530 and extended registerfile 535. Register file 530 may include separate register files forinteger and floating point operations. For purposes of configuration,control, and additional operations, a set of machine specific registers(MSRs) 538 may also be present and accessible to various logic withincore 500 (and external to the core). For example, power limitinformation may be stored in one or more MSR and be dynamically updatedas described herein.

Various resources may be present in execution units 520, including, forexample, various integer, floating point, and single instructionmultiple data (SIMD) logic units, among other specialized hardware. Forexample, such execution units may include one or more arithmetic logicunits (ALUs) 522 and one or more vector execution units 524, among othersuch execution units.

Results from the execution units may be provided to retirement logic,namely a reorder buffer (ROB) 540. More specifically, ROB 540 mayinclude various arrays and logic to receive information associated withinstructions that are executed. This information is then examined by ROB540 to determine whether the instructions can be validly retired andresult data committed to the architectural state of the processor, orwhether one or more exceptions occurred that prevent a proper retirementof the instructions. Of course, ROB 540 may handle other operationsassociated with retirement.

As shown in FIG. 5, ROB 540 is coupled to a cache 550 which, in oneembodiment may be a low level cache (e.g., an L1 cache) although thescope of the present invention is not limited in this regard. Also,execution units 520 can be directly coupled to cache 550. From cache550, data communication may occur with higher level caches, systemmemory and so forth. While shown with this high level in the embodimentof FIG. 5, understand the scope of the present invention is not limitedin this regard. For example, while the implementation of FIG. 5 is withregard to an out-of-order machine such as of an Intel® x86 instructionset architecture (ISA), the scope of the present invention is notlimited in this regard. That is, other embodiments may be implemented inan in-order processor, a reduced instruction set computing (RISC)processor such as an ARM-based processor, or a processor of another typeof ISA that can emulate instructions and operations of a different ISAvia an emulation engine and associated logic circuitry.

Referring now to FIG. 6, shown is a block diagram of amicro-architecture of a processor core in accordance with anotherembodiment. In the embodiment of FIG. 6, core 600 may be a low powercore of a different micro-architecture, such as an Intel® Atom™-basedprocessor having a relatively limited pipeline depth designed to reducepower consumption. As seen, core 600 includes an instruction cache 610coupled to provide instructions to an instruction decoder 615. A branchpredictor 605 may be coupled to instruction cache 610. Note thatinstruction cache 610 may further be coupled to another level of a cachememory, such as an L2 cache (not shown for ease of illustration in FIG.6). In turn, instruction decoder 615 provides decoded instructions to anissue queue 620 for storage and delivery to a given execution pipeline.A microcode ROM 618 is coupled to instruction decoder 615.

A floating point pipeline 630 includes a floating point register file632 which may include a plurality of architectural registers of a givenbit with such as 128, 256 or 512 bits. Pipeline 630 includes a floatingpoint scheduler 634 to schedule instructions for execution on one ofmultiple execution units of the pipeline. In the embodiment shown, suchexecution units include an ALU 635, a shuffle unit 636, and a floatingpoint adder 638. In turn, results generated in these execution units maybe provided back to buffers and/or registers of register file 632. Ofcourse understand while shown with these few example execution units,additional or different floating point execution units may be present inanother embodiment.

An integer pipeline 640 also may be provided. In the embodiment shown,pipeline 640 includes an integer register file 642 which may include aplurality of architectural registers of a given bit with such as 128 or256 bits. Pipeline 640 includes an integer scheduler 644 to scheduleinstructions for execution on one of multiple execution units of thepipeline. In the embodiment shown, such execution units include an ALU645, a shifter unit 646, and a jump execution unit 648. In turn, resultsgenerated in these execution units may be provided back to buffersand/or registers of register file 642. Of course understand while shownwith these few example execution units, additional or different integerexecution units may be present in another embodiment.

A memory execution scheduler 650 may schedule memory operations forexecution in an address generation unit 652, which is also coupled to aTLB 654. As seen, these structures may couple to a data cache 660, whichmay be a L0 and/or L1 data cache that in turn couples to additionallevels of a cache memory hierarchy, including an L2 cache memory.

To provide support for out-of-order execution, an allocator/renamer 670may be provided, in addition to a reorder buffer 680, which isconfigured to reorder instructions executed out of order for retirementin order. Although shown with this particular pipeline architecture inthe illustration of FIG. 6, understand that many variations andalternatives are possible.

Note that in a processor having asymmetric cores, such as in accordancewith the micro-architectures of FIGS. 5 and 6, workloads may bedynamically swapped between the cores for power management reasons, asthese cores, although having different pipeline designs and depths, maybe of the same or related ISA. Such dynamic core swapping may beperformed in a manner transparent to a user application (and possiblykernel also).

Referring to FIG. 7, shown is a block diagram of a micro-architecture ofa processor core in accordance with yet another embodiment. Asillustrated in FIG. 7, a core 700 may include a multi-staged in-orderpipeline to execute at very low power consumption levels. As one suchexample, processor 700 may have a micro-architecture in accordance withan ARM Cortex A53 design available from ARM Holdings, LTD., Sunnyvale,Calif. In an implementation, an 8-stage pipeline may be provided that isconfigured to execute both 32-bit and 64-bit code. Core 700 includes afetch unit 710 that is configured to fetch instructions and provide themto a decode unit 715, which may decode the instructions, e.g.,macro-instructions of a given ISA such as an ARMv8 ISA. Note furtherthat a queue 730 may couple to decode unit 715 to store decodedinstructions. Decoded instructions are provided to an issue logic 725,where the decoded instructions may be issued to a given one of multipleexecution units.

With further reference to FIG. 7, issue logic 725 may issue instructionsto one of multiple execution units. In the embodiment shown, theseexecution units include an integer unit 735, a multiply unit 740, afloating point/vector unit 750, a dual issue unit 760, and a load/storeunit 770. The results of these different execution units may be providedto a writeback unit 780. Understand that while a single writeback unitis shown for ease of illustration, in some implementations separatewriteback units may be associated with each of the execution units.Furthermore, understand that while each of the units and logic shown inFIG. 7 is represented at a high level, a particular implementation mayinclude more or different structures. A processor designed using one ormore cores having a pipeline as in FIG. 7 may be implemented in manydifferent end products, extending from mobile devices to server systems.

Referring to FIG. 8, shown is a block diagram of a micro-architecture ofa processor core in accordance with a still further embodiment. Asillustrated in FIG. 8, a core 800 may include a multi-stage multi-issueout-of-order pipeline to execute at very high performance levels (whichmay occur at higher power consumption levels than core 700 of FIG. 7).As one such example, processor 800 may have a microarchitecture inaccordance with an ARM Cortex A57 design. In an implementation, a 15 (orgreater)-stage pipeline may be provided that is configured to executeboth 32-bit and 64-bit code. In addition, the pipeline may provide for 3(or greater)-wide and 3 (or greater)-issue operation. Core 800 includesa fetch unit 810 that is configured to fetch instructions and providethem to a decoder/renamer/dispatcher 815, which may decode theinstructions, e.g., macro-instructions of an ARMv8 instruction setarchitecture, rename register references within the instructions, anddispatch the instructions (eventually) to a selected execution unit.Decoded instructions may be stored in a queue 825. Note that while asingle queue structure is shown for ease of illustration in FIG. 8,understand that separate queues may be provided for each of the multipledifferent types of execution units.

Also shown in FIG. 8 is an issue logic 830 from which decodedinstructions stored in queue 825 may be issued to a selected executionunit. Issue logic 830 also may be implemented in a particular embodimentwith a separate issue logic for each of the multiple different types ofexecution units to which issue logic 830 couples.

Decoded instructions may be issued to a given one of multiple executionunits. In the embodiment shown, these execution units include one ormore integer units 835, a multiply unit 840, a floating point/vectorunit 850, a branch unit 860, and a load/store unit 870. In anembodiment, floating point/vector unit 850 may be configured to handleSIMD or vector data of 128 or 256 bits. Still further, floatingpoint/vector execution unit 850 may perform IEEE-754 double precisionfloating-point operations. The results of these different executionunits may be provided to a writeback unit 880. Note that in someimplementations separate writeback units may be associated with each ofthe execution units. Furthermore, understand that while each of theunits and logic shown in FIG. 8 is represented at a high level, aparticular implementation may include more or different structures.

Note that in a processor having asymmetric cores, such as in accordancewith the micro-architectures of FIGS. 7 and 8, workloads may bedynamically swapped for power management reasons, as these cores,although having different pipeline designs and depths, may be of thesame or related ISA. Such dynamic core swapping may be performed in amanner transparent to a user application (and possibly kernel also).

A processor designed using one or more cores having pipelines as in anyone or more of FIGS. 5-8 may be implemented in many different endproducts, extending from mobile devices to server systems. Referring nowto FIG. 9, shown is a block diagram of a processor in accordance withanother embodiment of the present invention. In the embodiment of FIG.9, processor 900 may be a SoC including multiple domains, each of whichmay be controlled to operate at an independent operating voltage andoperating frequency. As a specific illustrative example, processor 900may be an Intel® Architecture Core™-based processor such as an i3, i5,i7 or another such processor available from Intel Corporation. However,other low power processors such as available from Advanced MicroDevices, Inc. (AMD) of Sunnyvale, Calif., an ARM-based design from ARMHoldings, Ltd. or licensee thereof or a MIPS-based design from MIPSTechnologies, Inc. of Sunnyvale, Calif., or their licensees or adoptersmay instead be present in other embodiments such as an Apple A7processor, a Qualcomm Snapdragon processor, or Texas Instruments OMAPprocessor. Such SoC may be used in a low power system such as asmartphone, tablet computer, phablet computer, Ultrabook™ computer orother portable computing device.

In the high level view shown in FIG. 9, processor 900 includes aplurality of core units 910 ₀-910 _(n). Each core unit may include oneor more processor cores, one or more cache memories and other circuitry.Each core unit 910 may support one or more instructions sets (e.g., anx86 instruction set (with some extensions that have been added withnewer versions); a MIPS instruction set; an ARM instruction set (withoptional additional extensions such as NEON)) or other instruction setor combinations thereof. Note that some of the core units may beheterogeneous resources (e.g., of a different design). In addition, eachsuch core may be coupled to a cache memory (not shown) which in anembodiment may be a shared level (L2) cache memory. A non-volatilestorage 930 may be used to store various program and other data. Forexample, this storage may be used to store at least portions ofmicrocode, boot information such as a BIOS, other system software or soforth.

Each core unit 910 may also include an interface such as a bus interfaceunit to enable interconnection to additional circuitry of the processor.In an embodiment, each core unit 910 couples to a coherent fabric thatmay act as a primary cache coherent on-die interconnect that in turncouples to a memory controller 935. In turn, memory controller 935controls communications with a memory such as a DRAM (not shown for easeof illustration in FIG. 9).

In addition to core units, additional processing engines are presentwithin the processor, including at least one graphics unit 920 which mayinclude one or more graphics processing units (GPUs) to perform graphicsprocessing as well as to possibly execute general purpose operations onthe graphics processor (so-called GPGPU operation). In addition, atleast one image signal processor 925 may be present. Signal processor925 may be configured to process incoming image data received from oneor more capture devices, either internal to the SoC or off-chip.

Other accelerators also may be present. In the illustration of FIG. 9, avideo coder 950 may perform coding operations including encoding anddecoding for video information, e.g., providing hardware accelerationsupport for high definition video content. A display controller 955further may be provided to accelerate display operations includingproviding support for internal and external displays of a system. Inaddition, a security processor 945 may be present to perform securityoperations such as secure boot operations, various cryptographyoperations and so forth.

Each of the units may have its power consumption controlled via a powermanager 940, which may include control logic to perform the variouspower management techniques described herein.

In some embodiments, SoC 900 may further include a non-coherent fabriccoupled to the coherent fabric to which various peripheral devices maycouple. One or more interfaces 960 a-960 d enable communication with oneor more off-chip devices. Such communications may be via a variety ofcommunication protocols such as PCIe™, GPIO, USB, I²C, UART, MIPI, SDIO,DDR, SPI, HDMI, among other types of communication protocols. Althoughshown at this high level in the embodiment of FIG. 9, understand thescope of the present invention is not limited in this regard.

Referring now to FIG. 10, shown is a block diagram of a representativeSoC. In the embodiment shown, SoC 1000 may be a multi-core SoCconfigured for low power operation to be optimized for incorporationinto a smartphone or other low power device such as a tablet computer orother portable computing device. As an example, SoC 1000 may beimplemented using asymmetric or different types of cores, such ascombinations of higher power and/or low power cores, e.g., out-of-ordercores and in-order cores. In different embodiments, these cores may bebased on an Intel® Architecture™ core design or an ARM architecturedesign. In yet other embodiments, a mix of Intel and ARM cores may beimplemented in a given SoC.

As seen in FIG. 10, SoC 1000 includes a first core domain 1010 having aplurality of first cores 1012 ₀-1012 ₃. In an example, these cores maybe low power cores such as in-order cores. In one embodiment these firstcores may be implemented as ARM Cortex A53 cores. In turn, these corescouple to a cache memory 1015 of core domain 1010. In addition, SoC 1000includes a second core domain 1020. In the illustration of FIG. 10,second core domain 1020 has a plurality of second cores 1022 ₀-1022 ₃.In an example, these cores may be higher power-consuming cores thanfirst cores 1012. In an embodiment, the second cores may be out-of-ordercores, which may be implemented as ARM Cortex A57 cores. In turn, thesecores couple to a cache memory 1025 of core domain 1020. Note that whilethe example shown in FIG. 10 includes 4 cores in each domain, understandthat more or fewer cores may be present in a given domain in otherexamples.

With further reference to FIG. 10, a graphics domain 1030 also isprovided, which may include one or more graphics processing units (GPUs)configured to independently execute graphics workloads, e.g., providedby one or more cores of core domains 1010 and 1020. As an example, GPUdomain 1030 may be used to provide display support for a variety ofscreen sizes, in addition to providing graphics and display renderingoperations.

As seen, the various domains couple to a coherent interconnect 1040,which in an embodiment may be a cache coherent interconnect fabric thatin turn couples to an integrated memory controller 1050. Coherentinterconnect 1040 may include a shared cache memory, such as an L3cache, in some examples. In an embodiment, memory controller 1050 may bea direct memory controller to provide for multiple channels ofcommunication with an off-chip memory, such as multiple channels of aDRAM (not shown for ease of illustration in FIG. 10).

In different examples, the number of the core domains may vary. Forexample, for a low power SoC suitable for incorporation into a mobilecomputing device, a limited number of core domains such as shown in FIG.10 may be present. Still further, in such low power SoCs, core domain1020 including higher power cores may have fewer numbers of such cores.For example, in one implementation two cores 1022 may be provided toenable operation at reduced power consumption levels. In addition, thedifferent core domains may also be coupled to an interrupt controller toenable dynamic swapping of workloads between the different domains.

In yet other embodiments, a greater number of core domains, as well asadditional optional IP logic may be present, in that an SoC can bescaled to higher performance (and power) levels for incorporation intoother computing devices, such as desktops, servers, high performancecomputing systems, base stations forth. As one such example, 4 coredomains each having a given number of out-of-order cores may beprovided. Still further, in addition to optional GPU support (which asan example may take the form of a GPGPU), one or more accelerators toprovide optimized hardware support for particular functions (e.g. webserving, network processing, switching or so forth) also may beprovided. In addition, an input/output interface may be present tocouple such accelerators to off-chip components.

Referring now to FIG. 11, shown is a block diagram of another exampleSoC. In the embodiment of FIG. 11, SoC 1100 may include variouscircuitry to enable high performance for multimedia applications,communications and other functions. As such, SoC 1100 is suitable forincorporation into a wide variety of portable and other devices, such assmartphones, tablet computers, smart TVs and so forth. In the exampleshown, SoC 1100 includes a central processor unit (CPU) domain 1110. Inan embodiment, a plurality of individual processor cores may be presentin CPU domain 1110. As one example, CPU domain 1110 may be a quad coreprocessor having 4 multithreaded cores. Such processors may behomogeneous or heterogeneous processors, e.g., a mix of low power andhigh power processor cores.

In turn, a GPU domain 1120 is provided to perform advanced graphicsprocessing in one or more GPUs to handle graphics and compute APIs. ADSP unit 1130 may provide one or more low power DSPs for handlinglow-power multimedia applications such as music playback, audio/videoand so forth, in addition to advanced calculations that may occur duringexecution of multimedia instructions. In turn, a communication unit 1140may include various components to provide connectivity via variouswireless protocols, such as cellular communications (including 3G/4GLTE), wireless local area protocols such as Bluetooth™, IEEE 802.11, andso forth.

Still further, a multimedia processor 1150 may be used to performcapture and playback of high definition video and audio content,including processing of user gestures. A sensor unit 1160 may include aplurality of sensors and/or a sensor controller to interface to variousoff-chip sensors present in a given platform. An image signal processor1170 may be provided with one or more separate ISPs to perform imageprocessing with regard to captured content from one or more cameras of aplatform, including still and video cameras.

A display processor 1180 may provide support for connection to a highdefinition display of a given pixel density, including the ability towirelessly communicate content for playback on such display. Stillfurther, a location unit 1190 may include a GPS receiver with supportfor multiple GPS constellations to provide applications highly accuratepositioning information obtained using as such GPS receiver. Understandthat while shown with this particular set of components in the exampleof FIG. 11, many variations and alternatives are possible.

Referring now to FIG. 12, shown is a block diagram of an example systemwith which embodiments can be used. As seen, system 1200 may be asmartphone or other wireless communicator. A baseband processor 1205 isconfigured to perform various signal processing with regard tocommunication signals to be transmitted from or received by the system.In turn, baseband processor 1205 is coupled to an application processor1210, which may be a main CPU of the system to execute an OS and othersystem software, in addition to user applications such as manywell-known social media and multimedia apps. Application processor 1210may further be configured to perform a variety of other computingoperations for the device.

In turn, application processor 1210 can couple to a userinterface/display 1220, e.g., a touch screen display. In addition,application processor 1210 may couple to a memory system including anon-volatile memory, namely a flash memory 1230 and a system memory,namely a dynamic random access memory (DRAM) 1235. As further seen,application processor 1210 further couples to a capture device 1240 suchas one or more image capture devices that can record video and/or stillimages.

Still referring to FIG. 12, a universal integrated circuit card (UICC)1240 comprising a subscriber identity module and possibly a securestorage and cryptoprocessor is also coupled to application processor1210. System 1200 may further include a security processor 1250 that maycouple to application processor 1210. A plurality of sensors 1225 maycouple to application processor 1210 to enable input of a variety ofsensed information such as accelerometer and other environmentalinformation. An audio output device 1295 may provide an interface tooutput sound, e.g., in the form of voice communications, played orstreaming audio data and so forth.

As further illustrated, a near field communication (NFC) contactlessinterface 1260 is provided that communicates in a NFC near field via anNFC antenna 1265. While separate antennae are shown in FIG. 12,understand that in some implementations one antenna or a different setof antennae may be provided to enable various wireless functionality.

A power management integrated circuit (PMIC) 1215 couples to applicationprocessor 1210 to perform platform level power management. To this end,PMIC 1215 may issue power management requests to application processor1210 to enter certain low power states as desired. Furthermore, based onplatform constraints, PMIC 1215 may also control the power level ofother components of system 1200.

To enable communications to be transmitted and received, variouscircuitry may be coupled between baseband processor 1205 and an antenna1290. Specifically, a radio frequency (RF) transceiver 1270 and awireless local area network (WLAN) transceiver 1275 may be present. Ingeneral, RF transceiver 1270 may be used to receive and transmitwireless data and calls according to a given wireless communicationprotocol such as 3G or 4G wireless communication protocol such as inaccordance with a code division multiple access (CDMA), global systemfor mobile communication (GSM), long term evolution (LTE) or otherprotocol. In addition a GPS sensor 1280 may be present. Other wirelesscommunications such as receipt or transmission of radio signals, e.g.,AM/FM and other signals may also be provided. In addition, via WLANtransceiver 1275, local wireless communications can also be realized.

Referring now to FIG. 13, shown is a block diagram of another examplesystem with which embodiments may be used. In the illustration of FIG.13, system 1300 may be mobile low-power system such as a tabletcomputer, 2:1 tablet, phablet or other convertible or standalone tabletsystem. As illustrated, a SoC 1310 is present and may be configured tooperate as an application processor for the device.

A variety of devices may couple to SoC 1310. In the illustration shown,a memory subsystem includes a flash memory 1340 and a DRAM 1345 coupledto SoC 1310. In addition, a touch panel 1320 is coupled to the SoC 1310to provide display capability and user input via touch, includingprovision of a virtual keyboard on a display of touch panel 1320. Toprovide wired network connectivity, SoC 1310 couples to an Ethernetinterface 1330. A peripheral hub 1325 is coupled to SoC 1310 to enableinterfacing with various peripheral devices, such as may be coupled tosystem 1300 by any of various ports or other connectors.

In addition to internal power management circuitry and functionalitywithin SoC 1310, a PMIC 1380 is coupled to SoC 1310 to provideplatform-based power management, e.g., based on whether the system ispowered by a battery 1390 or AC power via an AC adapter 1395. Inaddition to this power source-based power management, PMIC 1380 mayfurther perform platform power management activities based onenvironmental and usage conditions. Still further, PMIC 1380 maycommunicate control and status information to SoC 1310 to cause variouspower management actions within SoC 1310.

Still referring to FIG. 13, to provide for wireless capabilities, a WLANunit 1350 is coupled to SoC 1310 and in turn to an antenna 1355. Invarious implementations, WLAN unit 1350 may provide for communicationaccording to one or more wireless protocols.

As further illustrated, a plurality of sensors 1360 may couple to SoC1310. These sensors may include various accelerometer, environmental andother sensors, including user gesture sensors. Finally, an audio codec1365 is coupled to SoC 1310 to provide an interface to an audio outputdevice 1370. Of course understand that while shown with this particularimplementation in FIG. 13, many variations and alternatives arepossible.

Referring now to FIG. 14, shown is a block diagram of a representativecomputer system such as notebook, Ultrabook™ or other small form factorsystem. A processor 1410, in one embodiment, includes a microprocessor,multi-core processor, multithreaded processor, an ultra low voltageprocessor, an embedded processor, or other known processing element. Inthe illustrated implementation, processor 1410 acts as a main processingunit and central hub for communication with many of the variouscomponents of the system 1400. As one example, processor 1400 isimplemented as a SoC.

Processor 1410, in one embodiment, communicates with a system memory1415. As an illustrative example, the system memory 1415 is implementedvia multiple memory devices or modules to provide for a given amount ofsystem memory.

To provide for persistent storage of information such as data,applications, one or more operating systems and so forth, a mass storage1420 may also couple to processor 1410. In various embodiments, toenable a thinner and lighter system design as well as to improve systemresponsiveness, this mass storage may be implemented via a SSD or themass storage may primarily be implemented using a hard disk drive (HDD)with a smaller amount of SSD storage to act as a SSD cache to enablenon-volatile storage of context state and other such information duringpower down events so that a fast power up can occur on re-initiation ofsystem activities. Also shown in FIG. 14, a flash device 1422 may becoupled to processor 1410, e.g., via a serial peripheral interface(SPI). This flash device may provide for non-volatile storage of systemsoftware, including a basic input/output software (BIOS) as well asother firmware of the system.

Various input/output (I/O) devices may be present within system 1400.Specifically shown in the embodiment of FIG. 14 is a display 1424 whichmay be a high definition LCD or LED panel that further provides for atouch screen 1425. In one embodiment, display 1424 may be coupled toprocessor 1410 via a display interconnect that can be implemented as ahigh performance graphics interconnect. Touch screen 1425 may be coupledto processor 1410 via another interconnect, which in an embodiment canbe an I²C interconnect. As further shown in FIG. 14, in addition totouch screen 1425, user input by way of touch can also occur via a touchpad 1430 which may be configured within the chassis and may also becoupled to the same I²C interconnect as touch screen 1425.

For perceptual computing and other purposes, various sensors may bepresent within the system and may be coupled to processor 1410 indifferent manners. Certain inertial and environmental sensors may coupleto processor 1410 through a sensor hub 1440, e.g., via an I²Cinterconnect. In the embodiment shown in FIG. 14, these sensors mayinclude an accelerometer 1441, an ambient light sensor (ALS) 1442, acompass 1443 and a gyroscope 1444. Other environmental sensors mayinclude one or more thermal sensors 1446 which in some embodimentscouple to processor 1410 via a system management bus (SMBus) bus.

Also seen in FIG. 14, various peripheral devices may couple to processor1410 via a low pin count (LPC) interconnect. In the embodiment shown,various components can be coupled through an embedded controller 1435.Such components can include a keyboard 1436 (e.g., coupled via a PS2interface), a fan 1437, and a thermal sensor 1439. In some embodiments,touch pad 1430 may also couple to EC 1435 via a PS2 interface. Inaddition, a security processor such as a trusted platform module (TPM)1438 may also couple to processor 1410 via this LPC interconnect.

System 1400 can communicate with external devices in a variety ofmanners, including wirelessly. In the embodiment shown in FIG. 14,various wireless modules, each of which can correspond to a radioconfigured for a particular wireless communication protocol, arepresent. One manner for wireless communication in a short range such asa near field may be via a NFC unit 1445 which may communicate, in oneembodiment with processor 1410 via an SMBus. Note that via this NFC unit1445, devices in close proximity to each other can communicate.

As further seen in FIG. 14, additional wireless units can include othershort range wireless engines including a WLAN unit 1450 and a Bluetoothunit 1452. Using WLAN unit 1450, Wi-Fi™ communications can be realized,while via Bluetooth unit 1452, short range Bluetooth™ communications canoccur. These units may communicate with processor 1410 via a given link.

In addition, wireless wide area communications, e.g., according to acellular or other wireless wide area protocol, can occur via a WWAN unit1456 which in turn may couple to a subscriber identity module (SIM)1457. In addition, to enable receipt and use of location information, aGPS module 1455 may also be present. Note that in the embodiment shownin FIG. 14, WWAN unit 1456 and an integrated capture device such as acamera module 1454 may communicate via a given link.

An integrated camera module 1454 can be incorporated in the lid. Toprovide for audio inputs and outputs, an audio processor can beimplemented via a digital signal processor (DSP) 1460, which may coupleto processor 1410 via a high definition audio (HDA) link. Similarly, DSP1460 may communicate with an integrated coder/decoder (CODEC) andamplifier 1462 that in turn may couple to output speakers 1463 which maybe implemented within the chassis. Similarly, amplifier and CODEC 1462can be coupled to receive audio inputs from a microphone 1465 which inan embodiment can be implemented via dual array microphones (such as adigital microphone array) to provide for high quality audio inputs toenable voice-activated control of various operations within the system.Note also that audio outputs can be provided from amplifier/CODEC 1462to a headphone jack 1464. Although shown with these particularcomponents in the embodiment of FIG. 14, understand the scope of thepresent invention is not limited in this regard.

Embodiments may be implemented in many different system types. Referringnow to FIG. 15, shown is a block diagram of a system in accordance withan embodiment of the present invention. As shown in FIG. 15,multiprocessor system 1500 is a point-to-point interconnect system, andincludes a first processor 1570 and a second processor 1580 coupled viaa point-to-point interconnect 1550. As shown in FIG. 15, each ofprocessors 1570 and 1580 may be multicore processors, including firstand second processor cores (i.e., processor cores 1574 a and 1574 b andprocessor cores 1584 a and 1584 b), although potentially many more coresmay be present in the processors. Each of the processors can include aPCU or other power management logic to perform processor-based powermanagement as described herein.

Still referring to FIG. 15, first processor 1570 further includes amemory controller hub (MCH) 1572 and point-to-point (P-P) interfaces1576 and 1578. Similarly, second processor 1580 includes a MCH 1582 andP-P interfaces 1586 and 1588. As shown in FIG. 15, MCH's 1572 and 1582couple the processors to respective memories, namely a memory 1532 and amemory 1534, which may be portions of system memory (e.g., DRAM) locallyattached to the respective processors. First processor 1570 and secondprocessor 1580 may be coupled to a chipset 1590 via P-P interconnects1562 and 1564, respectively. As shown in FIG. 15, chipset 1590 includesP-P interfaces 1594 and 1598.

Furthermore, chipset 1590 includes an interface 1592 to couple chipset1590 with a high performance graphics engine 1538, by a P-P interconnect1539. In turn, chipset 1590 may be coupled to a first bus 1516 via aninterface 1596. As shown in FIG. 15, various input/output (I/O) devices1514 may be coupled to first bus 1516, along with a bus bridge 1518which couples first bus 1516 to a second bus 1520. Various devices maybe coupled to second bus 1520 including, for example, a keyboard/mouse1522, communication devices 1526 and a data storage unit 1528 such as adisk drive or other mass storage device which may include code 1530, inone embodiment. Further, an audio I/O 1524 may be coupled to second bus1520. Embodiments can be incorporated into other types of systemsincluding mobile devices such as a smart cellular telephone, tabletcomputer, netbook, Ultrabook™, or so forth.

A multi-chip package (MCP) may include a processor die (also processorchip herein) and a Platform Controller Hub (PCH) die (also PCH chipherein) in the same package. In order to ensure that both dies areprotected from prolonged exposure to high temperatures, the MCP may havea thermal management solution, e.g., management of power dissipated byone die based on a temperature of the other die. The terms “chip” and“die” are used interchangeably herein.

In embodiments, a mechanism is employed to enable one die to causethrottling (e.g., reduction) of power consumption in the other die.Triggering by one die of throttling in the other die may be achievedusing a pin-based die-to-die (e.g., chip-to-chip) connection. Such apin-based connection can be effective at high temperatures, during whichtransaction flows through a main band interconnect (e.g., distinct fromthe pin-based die-to-die connection) between the dies may not beguaranteed.

In embodiments, throttling of a first die may be initiated to reducetemperature of the first die, and throttling of a second die (e.g.,cross-die throttling) may be requested after a throttling limit of thefirst die is reached, e.g., additional throttling/power reduction is notpossible within the first die. After die throttling, cross-diethrottling provides an additional mechanism within the MCP to protectthe dies of the package against high temperature.

FIG. 16 is a block diagram of a system, according to embodiments of thepresent invention. The system 1600 is an MCP that includes two chips: afirst chip that is a processor chip 1610 (also processor herein), and asecond chip that is platform controller hub (PCH) chip 1640 (alsoplatform controller hub or PCH herein). The processor 1610 includes acore region 1620 and an uncore region 1630. The core region includes oneor more cores 1624. The core region 1620 also includes a cache memory1628, and may also include other modules (not shown), e.g., otherlogics. Each core 1624 _(i) may have at least one temperature sensor1626, situated proximate to the core 1624 _(i), to provide temperaturedata associated with the respective core 1624 _(i). There may beadditional temperature sensors 1626, situated at various locations inthe processor core region 1620 and the additional temperature sensors1626, may provide additional temperature data associated with otherfunctional units of the core region 1620. Other embodiments may haveless than one temperature sensor per core.

The uncore region 1630 may include one or more temperature sensors 1638(e.g., 1638 ₀-1638 _(m)) that may be situated at various locationswithin the uncore region 1630. The uncore region 1630 may also include apower management unit 1632 that may include temperature comparison andmanagement (TC/M) logic 1634, which may be implemented in hardware,e.g., a microcontroller, or in firmware, and/or software.

The PCH 1640 may include various control circuitry to control some datapaths (e.g., USB, PCIe, etc.) and support functions used in conjunctionwith the processor 1620. The PCH 1640 may include TC/M logic 1642, whichmay be implemented in hardware (e.g., a microcontroller), and/or infirmware, and/or in software. The PCH 1640 may also include one or moretemperature sensors 1644 that may be situated at various locationswithin the PCH.

The processor 1610 and the PCH 1640 may be coupled by a die-to-dieconduit 1650, such as a pin connecting the processor 1610 and the PCH1640. The die-to-die conduit 1650 may permit bi-directionalcommunication between dies and may be dedicated for transmission ofpower adjustment messages between the processor 1610 and the PCH 1640.The die-to-die conduit 1650 may be, e.g., a conductor such as metal, ormay be another dedicated pathway within the MCP 1600.

In operation, the TC/M logic 1634 may receive temperature data from thetemperature sensors 1626 and 1638. For instance, the temperature sensors1626 and 1638 may be polled periodically, aperiodically, or polling maybe triggered by an event. The TC/M logic 1634 may determine, from thetemperature data, whether a “hotspot” exists (e.g., a location ofexcessive temperature), e.g., a particular core 1624 _(z) that exceeds acore temperature threshold (e.g., the core temperature threshold may beset before operation of the system 1600, based on laboratory testsand/or known characteristics of the core 1624 _(z)). For example, theTC/M logic 1634 may compare received temperature data from one of thetemperature sensors 1626, to its respective temperature threshold, andif the temperature data exceeds the threshold, the associated core 1624_(z) may be identified as a hotspot.

In response to identification of a hotspot, various throttling measuresmay be invoked by the TC/M logic 1634 to reduce the temperature of thehotspot. Throttling measures may include reduction of core clockfrequency, reduction of core operating voltage, reduction in core dutycycle (e.g., percentage of operation time of the core 1624 _(z)), orother throttling measures. If a hotspot is detected within the uncoreregion 1630, throttling measures to be invoked may include reduction inclock frequency of the interconnect logic 1636 associated with aninterconnect, e.g., ring interconnect of the processor 1610.

If the temperature of the hotspot continues to exceed its temperaturethreshold after one or more throttling measures are invoked by the TC/Mlogic 1634, the TC/M logic 1634 may generate a first power adjustmentsignal, to be sent to the PCH 1640, e.g., via the die-to-die conduit1650. Upon receipt of the first power adjustment signal, the PCH 1640may reduce its power usage through, e.g., throttling within the PCH1640. For example, throttling within the PCH 1640 may include throttlingof activity in the PCH 1640 by, e.g., reduction of a clock frequency,reduction of an operating voltage, and/or reduction of a duty cycle ofthe PCH 1640.

If the TC/M logic 1634 detects that the temperature of the hotspot hasdecreased to a value less than or equal to the respective thresholdvalue, the TC/M logic 1634 may de-assert the first power adjustmentsignal. The PCH 1640 can cease throttling of activity and may resume alevel of activity (e.g., functionality) at which the PCH 1640 operatedprior to receipt of the first power adjustment signal.

Within the PCH 1640, TC/M logic 1642 may monitor temperature datareceived from one or more temperature sensors 1644 _(i). The TC/M logic1642 may conduct comparisons of temperature data received from each ofthe one or more temperature sensors 1644 _(i), to a respective thresholdvalue. If the TC/M logic 1642 detects that a temperature of a particularlocation within the PCH 1640 (as reflected in the temperature datareceived from a corresponding temperature sensor 1644 _(i)) exceeds therespective threshold value indicative of a hotspot condition within thePCH 1640, the TC/M logic 1642 may implement one or more throttlingmeasures in the PCH 1640, e.g., reduction in clock frequency, reductionin operating voltage, and/or reduction in duty cycle of the PCH 1640. Ifthe hotspot condition persists after the throttling measures areimplemented, the TC/M logic 1642 may generate a second power reductionsignal to be sent to the processor 1610 via the die-to-die conduit 1650.Responsive to receipt of the second power reduction signal, theprocessor 1610 may invoke one or more throttling techniques, e.g.,reduction in clock frequency of some or all of the cores, reduction ofoperating voltage of some or all of the cores, reduction in duty cycleof some or all of the cores, etc. in order to reduce heat generated bythe processor 1610, which may result in a reduction in operatingtemperature of the PCH 1640 within the MCP 1600. Thus, the temperatureof a hotspot within a first of the dies of an MCP, such as MCP 1600, canbe reduced by throttling actions within a second of the dies of the MCP.The throttling may be initiated by the first die that sends a poweradjustment signal to the second die via a die-to-die conduit that isdedicated for transmission of power adjustment signals.

In an embodiment, in order to evaluate the system following a change inoperating parameters, e.g., after one of the dies is throttled, a timedelay τ (relaxation time) may be invoked subsequent to the change inoperating parameters, after which temperature data is collected.

In other embodiments (not shown), the MCP may include three or morechips. The additional chips may be, e.g., memory chips, networkinterface (NIC) chips, or other chips. For example, there may be aprocessor and two additional chips in the MCP, and one dedicated pin(e.g., open-drain bi-directional pin) may couple the processor to eachof the additional chips, for communication of power reduction signalsbetween the processor and one or more of the additional chips, accordingto embodiments of the present invention. In one embodiment, responsiveto the processor exceeding a thermal threshold, the processor maytransmit a first power reduction signal to each of a second chip and athird chip. In another embodiment responsive to the processor exceedinga thermal threshold, the processor may transmit a first power reductionsignal to a first of the additional chips, and may transmit a secondpower reduction signal to a second of the additional chips.

In another embodiment, a measured temperature value of the processorthat exceeds a first thermal threshold may cause transmission of thefirst power reduction signal to the first additional chip, and when themeasured temperature value exceeds a second thermal threshold,transmission of a second power reduction signal to the second additionalchip may occur. After power reduction of the additional chip(s),responsive to detection that the measured temperature value is less thanor equal to the second thermal threshold, the second power reductionsignal may be de-asserted. Upon detection that the measured temperaturevalue is less than or equal to the first thermal threshold, the firstpower reduction signal and the second power reduction signal may bede-asserted.

FIG. 17 is a flow diagram of a method 1700, according to embodiments ofthe present invention. At block 1702, temperature sensors within aprocessor of an MCP are monitored by e.g., TC/M logic of the processor.Continuing to decision diamond 1704, if there are no processortemperature sensors whose measured temperature exceeds a respectivethreshold temperature, the method returns to block 1702. If thetemperature measured by one of the processor temperature sensors exceedsits respective threshold temperature, advancing to block 1706 the TC/Mlogic lowers the temperature of the core by throttling, e.g., frequencyand/or voltage reduction of a corresponding core, reduction of dutycycle, and/or reduction in uncore operating frequency of an uncore ofthe processor. For example, in one embodiment, an initial throttlingstage may include throttling of the frequency and/or voltage, which maybe followed in a second throttling stage by duty cycle reduction, andfinally in a third throttling stage by uncore frequency reduction. Foreach change implemented, the temperature of the hotspot may be monitored(e.g., after a relaxation time τ has passed) to determine whetheradditional throttling measures are to be implemented.

Moving to decision diamond 1708, if updated temperature data indicatethat no hotspots exist in the processor (e.g., none of the processorsensors have a temperature that exceeds a respective thresholdtemperature), proceeding to blocks 1720, 1722, and 1724, throttling ofuncore frequency, duty cycle, and frequency/voltage of one or more coresare de-asserted and each core is returned to operation according to itsoriginal operating parameters.

Back at decision block 1708, if one of the temperature sensors in theprocessor is above its threshold value, continuing to decision diamond1710 if the minimum duty cycle of the corresponding core has not beenreached, returning to block 1706 the duty cycle of the hotspot core isagain reduced, and following the reduction, proceeding to block 1708temperature data is again compared to the respective thresholdtemperature. If the hotspot condition persists and the minimum dutycycle is reached, advancing to block 1712, the TC/M logic of theprocessor asserts a throttle signal (temperature adjustment signal) to aPCH of the MCP via a die-to-die conduit that is dedicated for transportof temperature adjustment signals between dies of the MCP. The PCHreceives the throttle signal and may throttle its operation, e.g., byreduction of PCH clock frequency.

After the PCH is throttled, at decision block 1714 if temperature datafrom one of the processor temperature sensors indicates that the hotspotcondition persists, returning to block 1712 throttle signal remainsasserted and the temperature data from the processor temperature sensorscontinues to be monitored. When all of the temperature sensors of theprocessor indicate that no hotspot condition is present in theprocessor, advancing to block 1716 the TC/M logic de-asserts thethrottle signal sent to the PCH via the dedicated die-to-die conduit.Moving to block 1718, throttling of core frequency and voltage isde-asserted, duty cycle reduction of the cores is de-asserted, anduncore frequency reduction is de-asserted. Returning to block 1702, thetemperature sensors within the processor continue to be monitored forexcessive temperature.

FIG. 18 is a flow diagram of another method 1800, according toembodiments of the present invention. The method of FIG. 18 presents adetailed picture of throttling, according to an embodiment of thepresent invention.

At block 1802, temperature sensors of a processor of a first die withinan MCP are monitored. Continuing to block 1804, if any processortemperature sensors of the first die are above a (programmed) thresholdtemperature, advancing to decision diamond 1806 if the sensor whose dataindicates that it is above the respective threshold temperature islocated in a core region of the processor, moving to block 1808 afrequency and/or voltage of a core whose temperature (e.g., as indicatedby its respective temperature sensor) is above its respective thresholdtemperature, is throttled (e.g., reduced).

Advancing to decision diamond 1810, if any of the processor temperaturesensors persist in being greater than their respective thresholds, ifthe corresponding core is not yet operating at its lowest frequency andvoltage (as determined in decision diamond 1812), returning to block1808 an additional reduction of frequency and/or voltage is invoked.

If the hotspot(s) persist after operation of the respective core(s) attheir lowest operable frequency and voltage, proceeding to block 1814 aduty cycle of each hotspot core is reduced. Continuing to decisiondiamond 1816, if the hotspot(s) persist, the duty cycle is again reduced(at decision diamond 1818) if the smallest duty cycle has not beenreached. If the smallest duty cycle of the hotspot core has been reachedand the hotspot persists, advancing to block 1820 a frequency and/orvoltage of the uncore (e.g., interconnect logic) are reduced to theirsmallest operating values, and at decision diamond 1822 the temperaturesof the cores are again compared with their respective threshold values.If at decision diamond 1822 one or more processor temperatures are abovea respective threshold temperature, moving to block 1824 frequency andvoltage of all other cores of the first die are reduced. Proceeding todecision diamond 1826, if any of the processor temperature sensors isabove the threshold temperature (e.g., one or more hotspots persist),continuing to block 1840 a throttle signal is asserted, e.g., sent to asecond die of the MCP (e.g., a PCH) from the processor, e.g., via adedicated die-to-die conduit capable of two way communication betweenthe dies. The throttle signal is received by the PCH and throttling ofthe PCH ensues. Advancing to decision diamond 1842, if all of theprocessor temperature sensors indicate that their respectivetemperatures are less than or equal to their respective thresholdtemperature, proceeding to blocks 1844, 1846, and 1848, the throttlesignal to the PCH is de-asserted, the core and uncore frequencies andvoltages are re-instated, and the duty cycles of all cores arere-instated.

Back at decision diamond 1806, if one or more of the sensors that areabove their respective threshold levels are located in the uncore,continuing to block 1828 the uncore frequency and voltage are adjustedto their smallest operable values. Advancing to decision diamond 1830,if any hotspots persist in the uncore, moving to block 1832 thefrequency and voltage of all cores are reduced. If any hotspots persist(as determined in decision diamond 1834), proceeding to block 1836 theduty cycle of each core is reduced. Continuing to decision diamond 1838,if any hotspot persists, advancing to block 1840 the throttle signal isasserted to the second die (e.g., PCH) from the processor via thededicated die-to-die conduit. If any hotspots persist, returning toblock 1840 the throttle signal continues to be asserted in the PCH. Ifno hotspots persist after the PCH is throttled, at blocks 1844, 1846,1848, the PCH throttle signal is de-asserted, the core and uncorefrequencies and voltages are restored, and the duty cycle of each coreis restored.

At any point of the method, if all of the processor temperature sensorsare less than or equal to their respective thresholds, proceeding toblock 1844, a throttle signal previously asserted to the second die(PCH) of the MCP transmitted via, e.g., dedicated two-way pin isde-asserted and moving to block 1846, the core and uncore frequenciesand voltages are restored to pre-throttling levels. Advancing to block1848, the respective duty cycle of each core is restored to itspre-throttled duty cycle.

FIG. 19 is a flow diagram of another method 1900, according toembodiments of the present invention. At block 1902, one or moretemperature sensors are monitored in a second die (e.g., PCH chip) of anMCP that includes a first die (e.g., processor chip) and the second die.In other embodiments, the MCP may include additional chips.

Continuing to decision diamond 1904, if a PCH temperature T_(PCH) (e.g.,a largest measured value of the PCH temperature sensors) is less than afirst threshold temperature T_(th1), and if a first level of throttlingof the PCH had been previously asserted (e.g., due to an earlier hotspotcondition), at block 1936 the first level throttling is de-asserted.Returning to block 1902, monitoring of T_(PCH) continues.

If, at decision diamond 1904, T_(PCH) is greater than the firstthreshold temperature T_(th1), advancing to block 1906 the first levelof throttling is asserted in the PCH. For example, the first level ofthrottling may include reduction of a duty cycle of the PCH, e.g.,reduction of a percentage of active (e.g., “on”) time of the PCH. Movingto decision diamond 1908, if, after assertion of the first level ofthrottling, T_(PCH) is less than or equal to T_(th1) (e.g., as indicatedby the PCH temperature sensors), proceeding to block 1934 the firstlevel throttling is de-asserted, and returning to block 1902 monitoringof the PCH temperature T_(PCH) continues.

Again at decision diamond 1908, if T_(PCH) persists in being greaterthan T_(th1), as indicated by one or more of the PCH temperaturesensors, proceeding to decision diamond 1910 T_(PCH) is compared with asecond threshold temperature T_(th2) (e.g., greater than T_(th1)), andif T_(PCH) is less than or equal to T_(th2), returning to decisiondiamond 1904 if T_(PCH) is greater than T_(th1), continuing to block1906 first level throttling continues to be asserted.

If, at decision diamond 1910, T_(PCH) is greater than T_(th2),continuing to block 1912 a second level of throttling of the PCH (e.g.,greater than the first level of throttling of the PCH) is asserted.Advancing to decision diamond 1916, if T_(PCH) is less than or equal toT_(th2), moving to block 1932 the second level of throttling of the PCHis de-asserted, after which, proceeding to decision diamond 1904, it isdetermined whether T_(PCH) is greater than T_(th1). An outcome ofdecision diamond 1904 determines whether to continue to assert firstlevel throttling of the PCH, or to de-assert the first level throttlingof the PCH and return to block 1902 and continue to monitor T_(PCH).

Again at decision diamond 1916, if T_(PCH) is greater than T_(th2),proceeding to decision diamond 1918 if T_(PCH) is less than or equal toa third threshold temperature T_(th3), returning to block 1912 thesecond level of throttling of the PCH is asserted. If at decisiondiamond 1918, T_(PCH) is greater than T_(th3), a third level ofthrottling of the PCH is asserted at block 1920.

Continuing to decision diamond 1922, if T_(PCH) is greater than T_(th3),moving to decision diamond 1924 if T_(PCH) is greater than T_(PCH HOT)(e.g., a fourth threshold temperature, such as a highest safe operatingtemperature of the PCH), proceeding to block 1926 a throttle signal isasserted from the PCH to the first die (e.g., the processor chip), e.g.,via a two-way die-to-die conduit that is dedicated for transport oftemperature adjustment signals between the processor chip and the PCHchip of the MCP. After the throttle signal is asserted in the processor,at decision diamond 1928 if T_(PCH) continues to be greater thanT_(PCH HOT), the throttle signal to the processor chip continues to beasserted (block 1926). If, at decision diamond 1928, T_(PCH) is lessthan or equal to T_(PCH HOT), advancing to block 1930 the throttlesignal from the PCH to the processor is de-asserted and returning todecision diamond 1922, if T_(PCH) is greater than T_(th3) returning toblock 1920 the third level of throttling of the PCH continues to beasserted.

If, at decision diamond 1922, T_(PCH) is less than or equal to T_(th3),moving to block 1914 the third level of throttling is de-asserted, andreturning to decision diamond 1910 T_(PCH) is compared with T_(th2). IfT_(PCH) is greater than T_(th2) the second level of throttling continuesto be asserted, at block 1912. If T_(PCH) is less than or equal toT_(th2), the second level of throttling is de-asserted at block 1932,and T_(PCH) is compared with T_(th1), at decision diamond 1904. IfT_(PCH) is greater than T_(th1), the first level of throttling of thePCH is asserted, at block 1906. If T_(PCH) is less than or equal toT_(th1), moving to block 1936 the first level of throttling isde-asserted and returning to block 1902, temperature sensors continue tobe monitored in the PCH chip.

Additional embodiments are described below.

In a first example, a processor includes a first chip of a multi-chippackage (MCP). The first chip includes at least one core and first chiptemperature control (TC) logic to assert a first power adjustment signalat a second chip of the MCP responsive to an indication that a firstchip temperature of the first chip exceeds a first threshold. Theprocessor also includes a conduit including a bi-directional pin tocouple the first chip to a second chip within the MCP. The conduit is totransport the first power adjustment signal from the first chip to thesecond chip and the first power adjustment signal is to cause anadjustment of a second chip power consumption of the second chip.

In a second example that includes elements of the 1^(st) example, thefirst chip TC logic is to throttle at least one of the at least one coreresponsive to a first comparison that indicates that the first chiptemperature exceeds the first threshold, and after the at least one coreis throttled the first chip TC logic is to generate the first poweradjustment signal responsive to a second comparison that indicates thatthe first chip temperature continues to exceed the first threshold.

In a 3^(rd) example that includes elements of the 1^(st) example,adjustment of the second chip power consumption includes reduction ofpower consumed by the second chip.

In a 4^(th) example that includes elements of the 3^(rd) example, afterthe power consumed by the second chip is reduced, responsive to a thirdcomparison that indicates that the first chip temperature is less thanor equal to the first threshold, the first chip TC logic is to de-assertthe first power adjustment signal.

In a 5^(th) example that includes elements of the 1^(st) example, thefirst chip is to receive, via the conduit, a second power adjustmentsignal responsive to an indication that a second chip temperature of thesecond chip exceeds a second threshold. The second power adjustmentsignal, upon receipt by the first chip, is to result in adjustment of afirst chip power consumption of the first chip.

In a 6^(th) example that includes elements of the 5^(th) example, thefirst chip is to receive the second power adjustment signal from thesecond chip after the second chip has adjusted a second chip powerconsumption of the second chip and when after adjustment of the secondchip power consumption, the second chip temperature continues to exceedthe second threshold.

In a 7^(th) example that includes elements of the 5^(th) example, afterthe second power adjustment signal is received by the first chip,responsive to the second chip temperature being less than or equal tothe second threshold the second power adjustment signal is de-asserted.

An 8^(th) example any one of claims 1 to 7, the processor furtherincludes at least one temperature sensor to measure the first chiptemperature. The at least one temperature sensor is to be locatedproximate to the first chip.

A 9^(th) example is a multi-chip package (MCP) that includes a firstchip that includes a processor including at least one core, andtemperature control (TC) logic to generate a first power adjustmentsignal to be asserted at a second chip of the MCP responsive to a firstindication that a first chip temperature of the first chip exceeds afirst temperature threshold. The MCP also includes a conduit thatincludes a bi-directional pin to couple the first chip and the secondchip. The conduit is to transport the first power adjustment signal fromthe first chip to the second chip. The MCP also includes the second chipthat includes second chip logic to, responsive to receipt of the firstpower adjustment signal, adjust a second chip power consumption of thesecond chip.

A 10^(th) example includes elements of the 9^(th) example and furtherincludes a third chip coupled to the first chip via the conduit. Thefirst power adjustment signal is to be asserted, via the conduit, at thethird chip of the MCP responsive to the first indication that the firstchip temperature of the first chip exceeds the first temperaturethreshold, and responsive to receipt of the first power adjustmentsignal the third chip is to adjust a third chip power consumption of thethird chip.

An 11^(th) example includes elements of the 10^(th) example.Additionally, after the third chip power consumption is adjusted,responsive to a second indication that the first chip temperature isless than or equal to the first threshold, the TC logic is to de-assertthe first power adjustment signal.

A 12^(th) example includes any one of examples 9 to 11, where the secondchip logic is to adjust the second chip power consumption by throttlingsecond chip activity.

A 13^(th) example includes elements of any one of examples 9 to 11,where after the second chip power consumption is adjusted, responsive toa second indication that the first chip temperature is less than orequal to the first temperature threshold, the TC logic is to de-assertthe first power adjustment signal.

A 14^(th) example is a machine-readable medium having stored thereondata, which if used by at least one machine, causes the at least onemachine to fabricate at least one integrated circuit to perform a methodthat includes monitoring a first temperature of a first chip of amulti-chip processor (MCP), and responsive to a first indication thatthe first temperature exceeds a first threshold, throttling first chippower consumption of the first chip; after the first chip powerconsumption is throttled, responsive to a second indication that thefirst temperature continues to exceed the first threshold, asserting afirst power adjustment signal by the first chip and transmitting thefirst power adjustment signal to a second chip of the MCP via a conduitthat includes a bi-directional pin to couple the first chip and thesecond chip, and responsive to receipt by the second chip of the firstpower adjustment signal, second chip power consumption of the secondchip is throttled.

A 15^(th) example includes elements of the 14^(th) example. The methodfurther includes monitoring a second temperature associated with thesecond chip of the MCP, and responsive to the second temperature beinggreater than a second threshold, throttling, by the second chip, secondchip power consumption. The method includes responsive to the secondtemperature being greater than the second threshold after the secondchip power consumption is throttled, asserting a second power adjustmentsignal including transmitting the second power adjustment signal fromthe second chip to the first chip via the conduit, where upon receipt bythe first chip of the second power adjustment signal the first chippower consumption is to be throttled.

A 16^(th) example includes elements of the 15^(th) example. The methodfurther includes after the second power adjustment signal is transmittedand responsive to the second temperature being less than or equal to thesecond threshold, de-asserting the second power adjustment signal.

A 17^(th) example includes elements of any one of examples 14 to 16.Additionally, the method includes responsive to a third indication thatthe first temperature is less than or equal to the first threshold afterthe first power adjustment signal has been transmitted, de-asserting bythe first chip, the first power adjustment signal.

An 18^(th) example includes elements of any one of examples 14 to 16.The first chip includes a processor that includes a first core, andthrottling the first chip power consumption includes reduction of atleast one of a first core clock frequency of the first core and a firstcore operating voltage of the first core.

A 19^(th) example includes elements of any one of examples 14 to 16. Thefirst chip includes a processor that includes a first core, andthrottling the first chip power consumption includes reduction of a dutycycle of the first core.

A 20^(th) example includes elements of any one of examples 14 to 16. Thefirst chip includes a processor and throttling the first chip powerconsumption includes reduction of a clock frequency of an interconnectof the processor.

A 21^(st) example is a method that includes monitoring, by temperaturelogic within a first chip of a multi-chip package (MCP), a firsttemperature of the first chip, and responsive the first temperaturebeing greater than a first threshold reducing first chip powerconsumption of the first chip. The method includes after the first chippower consumption is reduced, determining whether the first temperaturecontinues to exceed the first threshold. The method includes responsiveto the first temperature being greater than the first threshold afterthe first chip power consumption is reduced, transmitting a first poweradjustment signal from the first chip to a second chip of the MCP via aconduit that includes a bi-directional pin to couple the first chip andthe second chip. The first power adjustment signal is to be asserted atthe second chip. The method includes responsive to assertion of thefirst power adjustment signal at the second chip, reducing second chippower consumption of the second chip.

A 22^(nd) example includes elements of the 21^(st) example. The methodfurther includes responsive to the first temperature being less than orequal to the first threshold after the first power adjustment signal hasbeen asserted, de-asserting the first power adjustment signal.

A 23^(rd) example includes elements of the 21^(st) example, and furtherincludes monitoring a second temperature of the second chip of the MCP,and responsive to the second temperature being greater than a secondthreshold reducing second chip power consumption of the second chip. Themethod further includes after the second chip power consumption isreduced, determining whether the second temperature continues to exceedthe second threshold, and responsive to the second temperature beinggreater than the second threshold after the second chip powerconsumption is reduced, transmitting a second power adjustment signalfrom the second chip to the first chip via the conduit to be asserted inthe first chip, where upon receipt by the first chip of the second poweradjustment signal the first chip power consumption is throttled.

A 24^(th) example includes elements of the 23^(rd) example, and furtherincludes after the second power adjustment signal is sent and responsiveto the second temperature being less than or equal to the secondthreshold, de-asserting the second power adjustment signal.

A 25^(th) example includes elements of any one of examples 21 to 24,where the first chip includes a processor that includes a first core,and where reducing the first chip power consumption includes at leastone of reduction of a first core clock frequency of the first core andreduction of a first core operating voltage of the first core.

A 26^(th) example includes elements of any one of examples 21 to 24,where the first chip includes a processor that includes a first core,and where reducing the first chip power consumption includes reductionof a duty cycle of the first core.

A 27^(th) example includes elements of any one of examples 21 to 24,where the first chip includes a processor, and wherein reducing thefirst chip power consumption includes reduction of a clock frequency ofan interconnect of the processor.

A 28^(th) example is an apparatus that includes means for performing themethod of any one of examples 21 to 24.

A 29^(th) example is an apparatus to perform the method of any one ofexamples 21 to 24.

A 30^(th) example is an apparatus that includes means for monitoring afirst temperature of a first chip of a multi-chip package (MCP), meansfor reducing first chip power consumption of the first chip responsiveto an indication that the first temperature exceeds a first threshold,means for determining whether the first temperature continues to exceedthe first threshold after the first chip power consumption is reduced,means for transmitting a first power adjustment signal from the firstchip to a second chip of the MCP via a conduit that comprises abi-directional pin to couple the first chip and the second chipresponsive to an indication that the first temperature continues toexceed the first threshold after the first chip power consumption isreduced, and means for reducing second chip power consumption of thesecond chip responsive to assertion of the first power adjustment signalat the second chip.

A 31^(st) example includes elements of the 30^(th) example, and furtherincludes means for de-asserting the first power adjustment signalresponsive to the first temperature being less than or equal to thefirst threshold after the first power adjustment signal has beentransmitted.

A 32^(nd) example includes elements of the 30^(th) example, and furtherincludes means for monitoring a second temperature of the second chip ofthe MCP, means for reducing second chip power consumption of the secondchip responsive to the second temperature being greater than a secondthreshold, means for determining whether the second temperaturecontinues to exceed the second threshold after the second chip powerconsumption is reduced, and means for transmitting a second poweradjustment signal from the second chip to the first chip via the conduitresponsive to the second temperature being greater than the secondthreshold after the second chip power consumption is throttled. Uponassertion at the first chip of the second power adjustment signal thefirst chip power consumption is to be reduced.

A 33^(rd) example includes elements of the 32^(nd) example, and furtherincludes means for de-asserting the second power adjustment signal afterthe second power adjustment signal is transmitted responsive to thesecond temperature being less than or equal to the second threshold.

A 34^(th) example includes elements of any one of examples 30 to 33.Additionally, the first chip includes a processor that includes a firstcore, and the means for reducing the first chip power consumptionincludes at least one of means for reducing a first core clock frequencyof the first core and means for reducing a first core operating voltageof the first core.

A 35^(th) example includes elements of any one of examples 30 to 33.Additionally, the first chip includes a processor that includes a firstcore, and the means for reducing the first chip power consumptionincludes means for reducing a duty cycle of the first core.

A 36^(th) example includes elements of any one of examples 30 to 33.Further, the first chip includes a processor, and the means for reducingthe first chip power consumption includes means for reducing a clockfrequency of an interconnect of the processor.

Embodiments may be used in many different types of systems. For example,in one embodiment a communication device can be arranged to perform thevarious methods and techniques described herein. Of course, the scope ofthe present invention is not limited to a communication device. Instead,other embodiments can be directed to other types of apparatus forprocessing instructions, or one or more machine readable media includinginstructions that in response to being executed on a computing device,cause the device to carry out one or more of the methods and techniquesdescribed herein, or one or more machine-readable media having storedthereon data, which if used by at least one machine, causes the at leastone machine to fabricate at least one integrated circuit to perform oneor more of the methods and/or techniques described herein.

Embodiments may be implemented in code and may be stored on anon-transitory storage medium having stored thereon instructions whichcan be used to program a system to perform the instructions. The storagemedium may include, but is not limited to, any type of disk includingfloppy disks, optical disks, solid state drives (SSDs), compact diskread-only memories (CD-ROMs), compact disk rewritables (CD-RWs), andmagneto-optical disks, semiconductor devices such as read-only memories(ROMs), random access memories (RAMs) such as dynamic random accessmemories (DRAMs), static random access memories (SRAMs), erasableprogrammable read-only memories (EPROMs), flash memories, electricallyerasable programmable read-only memories (EEPROMs), magnetic or opticalcards, or any other type of media suitable for storing electronicinstructions.

While the present invention has been described with respect to a limitednumber of embodiments, those skilled in the art will appreciate numerousmodifications and variations therefrom. It is intended that the appendedclaims cover all such modifications and variations as fall within thetrue spirit and scope of this present invention.

What is claimed is:
 1. A processor comprising: a first chip of amulti-chip package (MCP), wherein the first chip includes at least onecore and first chip temperature control (TC) logic to assert a firstpower adjustment signal at a second chip of the MCP responsive to anindication that a first chip temperature of the first chip exceeds afirst threshold; and a conduit comprising a bi-directional pin to couplethe first chip to the second chip within the MCP, wherein the conduit isto transport the first power adjustment signal from the first chip tothe second chip and the first power adjustment signal is to cause anadjustment of a second chip power consumption of the second chip.